The high efficiency of switching power converters such as flyback converters has led to their widespread adaption as the battery charger for mobile devices. In a flyback converter, a controller controls the cycling of a power switch transistor that connects between the transformer's primary winding and ground. A rectified AC mains voltage such as from a bridge diode rectifier drives the primary winding current when the power switch is cycled on. The rectified AC mains voltage can be several hundred volts such that it can stress the power switch transistor. To minimize the switching stress for the power switch transistor, it is known to employ valley switching techniques with regard to the resonant oscillation of the drain voltage for the power switch transistor when it is cycled off. The peak voltages for the resonant oscillation can be relatively robust (as much as 200 V or higher) whereas the minimum voltages (the valleys in the resonant oscillations) are much lower.
Valley mode switching may be better understood through a consideration of the waveforms shown in FIG. 1. At a time t1, a power switch transistor S1 is cycled on and then cycled off at a time t2. The drain voltage (V_DRAIN) for power switch transistor S1 is grounded while it is on. A secondary winding current does not flow while the power switch transistor S1 is on. At time t2, the drain voltage abruptly rises high in response to the cycling off of the power switch transistor S. The secondary winding current then jumps high and begins to ramp down to zero at a time t3, which is denoted as the transformer reset time. From time t2 to time t3, the drain voltage slowly declines from its high value and then drops at the transformer reset time, whereupon the drain voltage begins resonantly oscillating. Each minimum or valley in the resonant oscillation is numbered, starting from an initial valley 1 to a fourth valley 4 at a time t4. Another power switch cycle is started at time t4. But since the drain voltage equals its local minimum at valley 4, the stress to the power switch transistor S1 is minimized due to the resulting valley-mode switching. A similar reduction in stress would occur if the on-time for the power switch transistor S1 occurred at an earlier or later valley.
Although valley-mode switching thus lowers the voltage stress on the power switch transistor, note that the valley voltages are not zero but may range to 20 V or even higher such as 60 V. This relatively high drain voltage is then discharged to ground when the power switch transistor is cycled on, which lowers efficiency. A more power-efficient alternative to valley-mode switching is zero-voltage-switching (ZVS). In ZVS operation, the leakage energy in the transformer is stored and reclaimed in a capacitor that is coupled to the drain voltage of the power switch transistor through an active clamp switch. The active clamp switch is cycled on at the peak of the resonant oscillations, whereupon the drain voltage is discharged to ground as the leakage energy is reclaimed. An ZVS architecture thus has no stressing switches at the on-time of the power switch transistor.
A valley-mode controller thus needs some means of detecting the valleys in the resonant oscillations of the drain voltage whereas a ZVS controller needs a means for detecting the peaks in such resonant oscillations. In addition, a ZVS controller needs a means for detecting a zero crossing for the drain voltage. However, existing valley and peak detection schemes are prone to inaccuracies.
For example, an estimate may be made of the period T for the resonant oscillations based upon an estimate of the inductance for the primary winding and the parasitic capacitance for the power switch transistor. A valley may then be deemed to occur after a T/4 delay from the midpoint crossing of a falling edge for the resonant oscillations such as detected through a comparator. Similarly, a peak may be deemed to occur after a T/4 delay from the midpoint crossing of a rising edge for the resonant oscillations. But these parasitic elements will vary from component to component and thus from one flyback converter to another such that a fixed estimate of the period T will lead to inaccurate peak and valley detection.
It is thus known to adaptively measure the ringing frequency period for the drain voltage to estimate the peak and valley locations. Some exemplary waveforms for a conventional adaptive technique are shown in FIG. 2. A comparator compares the drain voltage to a comparator threshold voltage that equals the common-mode voltage (mid-point voltage) for the resonant ringing of the drain voltage. The low time (or the high time) for the comparator output equals ½ the resonant period T. The resulting flyback controller may thus use a counter that counts T/4 after the low transition of the comparator output signal to estimate the valley location. Conversely, the controller may estimate that a peak occurs after a delay of T/4 from the comparator rising edge. Although such an adaptive approach does not suffer from the process variations of a fixed approach, note that it requires the complexity of a counter. More fundamentally, it does not directly detect the peaks and valleys but instead estimates their location. But such an estimation assumes that the peaks and valleys are symmetric. In reality, the peaks and valleys are subject to non-linearities and noise such that even if the period T is measured accurately, the resulting estimation is prone to inaccuracies. These inaccuracies are aggravated as the switching frequency is increased in modern flyback converters because the primary winding inductance is lowered at increased switching frequencies such that the resonant oscillation period T is reduced accordingly.
Accordingly, there is a need in the art for improved valley and peak detection methods and circuits for switching power converters.